1. Field of the Invention
The present invention relates to a method of manufacturing a silicon wafer and a silicon wafer, in particular to a method of manufacturing a silicon wafer using a laser spike anneal process.
2. Description of the Related Art
It is important for a surface layer part of a silicon wafer for manufacturing a device to have substantially no defects in order to improve electrical characteristics of the wafer, especially an oxide film withstand voltage characteristic.
Usually, in most cases, a void type defect (also referred to as a grown-in defect) referred to as COP (Crystal Originated Particle) introduced at the time of crystal growth exists in the surface layer part of the silicon wafer manufactured by way of Czochralski method (the CZ method).
Such a void type defect existing in the surface layer part of the silicon wafer damages an oxide film withstand voltage characteristic and may be a reason for adversely affecting an electrical property of the semiconductor device formed at the wafer. For this reason, especially in recent years, there is a strong need for a wafer having a defectless surface layer in which there is no such a defect at the surface layer, thus using a Si/Si epitaxial growth wafer in which a silicon epitaxial growth film is provided on the wafer surface, a wafer manufactured by way of a reduced growth rate at the time of growing a single crystal, etc.
However, there is a problem in that such a wafer has poor productivity and is very costly.
Then, for example, patent document 1 (Japanese Patent No. 3346249), patent document 2 (Japanese Patent No. 3410828), and patent document 3 (Japanese Patent Publication (KOKAI) No. 2005-123241 propose that, in order to improve the oxide film withstand voltage characteristic of a silicon wafer and to raise productivity, a silicon wafer should be heat-treated in a hydrogen and argon gas atmosphere by way of a method called rapid heating and rapid quench thermal treatment (Rapid Thermal Annealing: RTA).
As already described, the silicon wafer grown by using the CZ method has the defects (grown-in defects) introduced into its surface and inside at the time of growing the crystal. This grown-in defect has an octahedral structure when it is inside the crystal. In the case where the grown-in defect is exposed to the surface after being formed into the wafer, it is observed as a concave pit of a pyramid form, and an oxide film having a thickness of several nm is formed on a wall of the concave pit.
The hydrogen atmosphere as disclosed in the above-mentioned patent documents 1-3 allows removal of the inner wall oxide film of the grown-in defect exposed to the wafer surface by way of RTA process for the silicon wafer.
In addition, when the wafer is heated to a high temperature in such an RTA process, inter-lattice silicon (Si) and point defects of cavities take place inside the wafer at a high concentration.
Then, rapid quench (cooling) of the wafer causes the point defects to be excessive and diffuse outwards to the wafer surface. At this time, as inter-lattice silicon diffuses externally which has a large diffusion coefficient in the crystal and quickly diffuses, the inter-lattice silicon is captured by the grown-in defect on the surface of the wafer. Thus the grown-in defects are filled. As a result, the grown-in defects which exist in the wafer surface can be reduced.
In such rapid heating and rapid quench thermal treatment process (RTA process), it is often the case that an apparatus is used in which a silicon wafer is laid within a bell jar type container made of quartz, silicon carbide (for example), and a lamp heating system by means of a halogen lamp etc. is employed as a source of heating.
Therefore, since the process is carried out by using such an apparatus, the processing conditions are usually such that a rise-and-fall speed in temperature is 150° C./sec or less, a heat treatment temperature is 1200° C.-1350° C., and a period of time is 10 seconds or more.
However, when the rise speed in temperature is equal to or less than 150° C./sec within the above-mentioned range of the heat treatment temperature, the inter-lattice Si out of the inter-lattice silicon (Si) and the cavity generated due to the rising temperature is emitted towards the wafer surface by diffusion., Thus, the grown-in defect on the above-mentioned surface of the wafer is removed, but the grown-in defect existing inside the wafer surface layer cannot be removed, which results in a disadvantage that the grown-in defect remains in a device activity layer of the wafer surface layer part.